CY7C1650KV18-450BZC
制造商:
物料参数
| Architecture: | DDR-II+ CIO |
| Bank Switching: | N |
| Burst Length(Words): | 2 |
| Data Width: | x 36 |
| Family: | DDR-II+ CIO |
| Frequency: | 450.0MHz |
| Lead Ball Finish: | Sn/Pb |
| On-Die Termination: | N |
| Operating Temperature: | None°C |
| Organization (X x Y): | 4Mb x 36 |
| Qualification: | Commercial |
| Read Latency (Cycles): | 2.0 |
| ECC: | N |
| Peak Reflow Temp: | 260.0°C |
| Operating Voltage: | NoneV |
| Interfaces: | Parallel |
| Density: | 147456.0kBit |
| Density: | 144.0MBit |
无库存