CY7C1625KV18-333BZXC

制造商:

物料参数

Architecture:QDR-II
Bank Switching:N
Burst Length(Words):2
Data Width:x 9
Family:QDR-II
Frequency:333.0MHz
Lead Ball Finish:Sn/Ag/Cu
On-Die Termination:N
Operating Temperature:None°C
Organization (X x Y):16Mb x 9
Peak Reflow Temp:260.0°C
Qualification:Commercial
Read Latency (Cycles):1.5
ECC:N
Operating Voltage:NoneV
Interfaces:Parallel
Density:147456.0kBit
Density:144.0MBit
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