CY7C15632KV18-400BZXC

制造商:

物料参数

Architecture:QDR-II+
Bank Switching:N
Burst Length(Words):4
ECC:N
Family:QDR-II+
Frequency:400.0MHz
Lead Ball Finish:Sn/Ag/Cu
On-Die Termination:N
Operating Temperature:None°C
Organization (X x Y):4Mb x 18
Peak Reflow Temp:260.0°C
Read Latency (Cycles):2.5
Data Width:x 18
Qualification:Commercial
Operating Voltage:NoneV
Interfaces:Parallel
Density:73728.0kBit
Density:72.0MBit
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