CY7C1360D-1XWI
制造商:
物料参数
| Architecture: | Standard Sync, Pipeline SCD |
| Bank Switching: | N |
| Data Width: | x 36 |
| Family: | Standard Sync |
| Lead Ball Finish: | None |
| On-Die Termination: | N |
| Operating Temperature: | None°C |
| Operating Voltage(VCCQ): | NoneV |
| Operating Voltage: | NoneV |
| Organization (X x Y): | 256Kb x 36 |
| Qualification: | Industrial |
| ECC: | N |
| Read Latency (Cycles): | 1.0 |
| Interfaces: | Parallel |
| Density: | 9216.0kBit |
| Density: | 9.0MBit |
无库存