CY7C2564XV18-450BZXC

制造商:

物料参数

Architecture:QDR-II+ Xtreme
Bank Switching:N
Burst Length(Words):2
Data Width:x 36
Family:QDR-II+ Xtreme
Lead Ball Finish:Sn/Ag/Cu
On-Die Termination:Y
Operating Temperature:None°C
Organization (X x Y):2Mb x 36
Peak Reflow Temp:260.0°C
Qualification:Commercial
Read Latency (Cycles):2.5
ECC:N
Frequency:450.0MHz
Operating Voltage:NoneV
Interfaces:Parallel
Density:73728.0kBit
Density:72.0MBit
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