CY7C1262XV18-450BZXC
制造商:
物料参数
| Architecture: | QDR-II+ Xtreme |
| Bank Switching: | N |
| Burst Length(Words): | 2 |
| Data Width: | x 18 |
| ECC: | N |
| Family: | QDR-II+ Xtreme |
| Frequency: | 450.0MHz |
| Lead Ball Finish: | Sn/Ag/Cu |
| Operating Temperature: | None°C |
| Peak Reflow Temp: | 260.0°C |
| Qualification: | Commercial |
| Read Latency (Cycles): | 2.5 |
| On-Die Termination: | N |
| Organization (X x Y): | 2Mb x 18 |
| Operating Voltage: | NoneV |
| Interfaces: | Parallel |
| Density: | 36864.0kBit |
| Density: | 36.0MBit |
无库存