物料参数
| Architecture: | QDR-IV |
| Bank Switching: | N |
| ECC: | Y |
| Family: | QDR-IV |
| Frequency: | 633.0MHz |
| Lead Ball Finish: | Sn/Ag/Cu |
| On-Die Termination: | Y |
| Operating Temperature max: | 85.0°C |
| Organization (X x Y): | 8Mb x 18 |
| Peak Reflow Temp: | 260.0°C |
| Qualification: | Industrial |
| Read Latency (Cycles): | 5.0 |
| Data Width: | x 18 |
| Burst Length(Words): | 2 |
| Operating Voltage max: | 1.34V |
| Interfaces: | Parallel |
| Density: | 144.0MBit |
