物料参数
| Architecture: | QDR-II+ |
| Bank Switching: | N |
| Data Width: | x 18 |
| Family: | QDR-II+ |
| Frequency: | 250.0MHz |
| Lead Ball Finish: | Sn/Pb |
| On-Die Termination: | N |
| Organization (X x Y): | 2Mb x 36 |
| Qualification: | Military |
| Read Latency (Cycles): | 2.0 |
| ECC: | N |
| Operating Temperature: | None°C |
| Burst Length(Words): | 2 |
| Operating Voltage: | NoneV |
| Interfaces: | Parallel |
| Peak Reflow Temp: | 220.0°C |
| Density: | 73728.0kBit |
| Density: | 72.0MBit |