Architecture: QDR-II+ Xtreme Bank Switching: N Burst Length(Words): 4 ECC: N Family: QDR-II+ Xtreme Lead Ball Finish: Sn/Ag/Cu On-Die Termination: Y Operating Temperature: None°C Organization (X x Y): 4Mb x 18 Peak Reflow Temp: 260.0°C Read Latency (Cycles): 2.5 Data Width: x 18 Frequency: 600.0MHz Qualification: Commercial Operating Voltage: NoneV Interfaces: Parallel Density: 73728.0kBit Density: 72.0MBit

Lead Ball Finish: Sn/Pb Operating Temperature: None°C Operating Voltage: NoneV Peak Reflow Temp: 260.0°C Family: QDR-II Interfaces: Parallel Frequency: 250.0MHz Organization (X x Y): 4M x 18 Qualification: Commercial Density: 72.0MBit

Architecture: QDR-II+, ODT Burst Length(Words): 4 ECC: N Family: QDR-II+, ODT Frequency: 400.0MHz Lead Ball Finish: Sn/Pb On-Die Termination: Y Operating Temperature: None°C Organization (X x Y): 4Mb x 18 Peak Reflow Temp: 260.0°C Read Latency (Cycles): 2.5 Data Width: x 18 Bank Switching: N Qualification: Commercial Operating Voltage: NoneV Interfaces: Parallel Density: 73728.0kBit Density: 72.0MBit

Architecture: NoBL, Pipeline Bank Switching: N Data Width: x 18 ECC: N On-Die Termination: N Operating Temperature: None°C Organization (X x Y): 512Kb x 18 Qualification: Industrial Read Latency (Cycles): 1.0 Peak Reflow Temp: 260.0°C Family: NoBL Frequency: 166.0MHz Lead Ball Finish: Ni/Pd/Au Operating Voltage: NoneV Interfaces: Parallel Density: 9216.0kBit Density: 9.0MBit

Bank Switching: N Burst Length(Words): 4 Data Width: x 36 ECC: N Family: QDR-II+, ODT Frequency: 550.0MHz Lead Ball Finish: Sn/Ag/Cu On-Die Termination: Y Operating Temperature: None°C Peak Reflow Temp: 260.0°C Qualification: Commercial Read Latency (Cycles): 2.5 Architecture: QDR-II+, ODT Organization (X x Y): 1Mb x 36 Operating Voltage: NoneV Interfaces: Parallel Density: 36864.0kBit Density: 36.0MBit

Family: QDR-II Operating Voltage: NoneV Peak Reflow Temp: 260.0°C Operating Temperature: None°C Lead Ball Finish: Sn/Ag/Cu Interfaces: Parallel Frequency: 250.0MHz Organization (X x Y): 4M x 18 Qualification: Industrial Density: 72.0MBit

Architecture: QDR-II Bank Switching: N Burst Length(Words): 4 Data Width: x 36 Family: QDR-II Frequency: 300.0MHz Lead Ball Finish: Sn/Pb On-Die Termination: N Operating Temperature: None°C Organization (X x Y): 2Mb x 36 Peak Reflow Temp: 260.0°C Read Latency (Cycles): 1.5 ECC: N Qualification: Commercial Operating Voltage: NoneV Interfaces: Parallel Density: 73728.0kBit Density: 72.0MBit

Architecture: Standard Sync, Pipeline DCD Bank Switching: N Burst Length(Words): 4 ECC: N Family: Standard Sync Frequency: 167.0MHz Lead Ball Finish: Pure Sn On-Die Termination: N Operating Temperature: None°C Organization (X x Y): 1Mb x 18 Peak Reflow Temp: 260.0°C Qualification: Commercial Read Latency (Cycles): 2.0 Data Width: x 18 Operating Voltage: NoneV Interfaces: Parallel Density: 18432.0kBit Density: 18.0MBit

Lead Ball Finish: Sn/Pb Operating Temperature: None°C Operating Voltage: NoneV Peak Reflow Temp: 260.0°C Family: QDR-II+, ODT Interfaces: Parallel Frequency: 450.0MHz Organization (X x Y): 4M x 18 Qualification: Commercial Density: 72.0MBit

Architecture: QDR-IV Bank Switching: Y Burst Length(Words): 2 Data Width: x 36 Family: QDR-IV Lead Ball Finish: Sn/Ag/Cu On-Die Termination: Y Organization (X x Y): 2Mb x 36 Peak Reflow Temp: 260.0°C Qualification: Commercial Read Latency (Cycles): 8.0 ECC: Y Operating Temperature: None°C Frequency: 933.0MHz Operating Voltage: NoneV Interfaces: Parallel Density: 73728.0kBit Density: 72.0MBit