Architecture: QDR-II+ Bank Switching: N Burst Length(Words): 4 ECC: N Family: QDR-II+ Lead Ball Finish: Sn/Ag/Cu On-Die Termination: N Operating Temperature: None°C Organization (X x Y): 8Mb x 18 Peak Reflow Temp: 260.0°C Qualification: Commercial Read Latency (Cycles): 2.5 Data Width: x 18 Frequency: 550.0MHz Operating Voltage: NoneV Interfaces: Parallel Density: 147456.0kBit Density: 144.0MBit

Architecture: QDR-II+ Data Width: x 18 ECC: N Frequency: 550.0MHz Lead Ball Finish: Sn/Ag/Cu On-Die Termination: N Operating Temperature: None°C Organization (X x Y): 8Mb x 18 Qualification: Industrial Read Latency (Cycles): 2.5 Bank Switching: N Family: QDR-II+ Peak Reflow Temp: 260.0°C Burst Length(Words): 4 Operating Voltage: NoneV Interfaces: Parallel Density: 147456.0kBit Density: 144.0MBit

Architecture: QDR-II+ Xtreme Bank Switching: N Burst Length(Words): 2 Data Width: x 18 ECC: N Family: QDR-II+ Xtreme Frequency: 450.0MHz Lead Ball Finish: Sn/Ag/Cu Operating Temperature: None°C Peak Reflow Temp: 260.0°C Qualification: Commercial Read Latency (Cycles): 2.5 On-Die Termination: N Organization (X x Y): 2Mb x 18 Operating Voltage: NoneV Interfaces: Parallel Density: 36864.0kBit Density: 36.0MBit

Family: QDR-II Operating Voltage: NoneV Peak Reflow Temp: 260.0°C Lead Ball Finish: Sn/Ag/Cu Operating Temperature: None°C Interfaces: Parallel Frequency: 300.0MHz Organization (X x Y): 4M x 18 Qualification: Industrial Density: 72.0MBit

Architecture: NoBL, Pipeline Data Width: x 36 ECC: N Family: NoBL Frequency: 167.0MHz On-Die Termination: N Operating Temperature: None°C Organization (X x Y): 2Mb x 36 Qualification: Industrial Read Latency (Cycles): 1.0 Bank Switching: N Peak Reflow Temp: 260.0°C Lead Ball Finish: Pure Sn Operating Voltage: NoneV Interfaces: Parallel Density: 73728.0kBit Density: 72.0MBit

Architecture: NoBL, Flow-through Data Width: x 36 Family: NoBL On-Die Termination: N Operating Temperature: None°C Organization (X x Y): 2Mb x 36 Peak Reflow Temp: 260.0°C Qualification: Commercial ECC: N Frequency: 133.0MHz Bank Switching: N Lead Ball Finish: Pure Sn Operating Voltage: NoneV Interfaces: Parallel Density: 73728.0kBit Density: 72.0MBit

Family: QDR-II+ Lead Ball Finish: Sn/Ag/Cu Operating Temperature: None°C Operating Voltage: NoneV Peak Reflow Temp: 260.0°C Interfaces: Parallel Frequency: 500.0MHz Organization (X x Y): 4M x 18 Qualification: Industrial Density: 72.0MBit

Architecture: QDR-II+ Xtreme Bank Switching: N Burst Length(Words): 2 Data Width: x 18 ECC: N Frequency: 366.0MHz Lead Ball Finish: Sn/Ag/Cu On-Die Termination: N Operating Temperature: None°C Organization (X x Y): 2Mb x 18 Peak Reflow Temp: 260.0°C Read Latency (Cycles): 2.5 Family: QDR-II+ Xtreme Qualification: Commercial Operating Voltage: NoneV Interfaces: Parallel Density: 36864.0kBit Density: 36.0MBit

Bank Switching: N Data Width: x 36 ECC: N Family: Standard Sync Frequency: 250.0MHz Lead Ball Finish: Sn/Pb On-Die Termination: N Operating Temperature: None°C Organization (X x Y): 2Mb x 36 Peak Reflow Temp: 220.0°C Qualification: Industrial Read Latency (Cycles): 1.0 Architecture: Standard Sync, Pipeline SCD Operating Voltage: NoneV Interfaces: Parallel Density: 73728.0kBit Density: 72.0MBit

Bank Switching: N Burst Length(Words): 4 ECC: N Family: QDR-II+, ODT Lead Ball Finish: Sn/Ag/Cu On-Die Termination: Y Operating Temperature: None°C Organization (X x Y): 8Mb x 18 Peak Reflow Temp: 260.0°C Qualification: Commercial Read Latency (Cycles): 2.5 Data Width: x 18 Frequency: 550.0MHz Architecture: QDR-II+, ODT Operating Voltage: NoneV Interfaces: Parallel Density: 147456.0kBit Density: 144.0MBit