Architecture: QDR-II+, ODT Bank Switching: N ECC: N Family: QDR-II+, ODT Frequency: 333.0MHz Lead Ball Finish: Sn/Ag/Cu On-Die Termination: Y Operating Temperature: None°C Organization (X x Y): 4Mb x 36 Peak Reflow Temp: 260.0°C Qualification: Industrial Read Latency (Cycles): 2.5 Data Width: x 36 Burst Length(Words): 2 Operating Voltage: NoneV Interfaces: Parallel Density: 147456.0kBit Density: 144.0MBit

Family: QDR-II+, ODT Lead Ball Finish: Sn/Ag/Cu Operating Voltage: NoneV Peak Reflow Temp: 260.0°C Operating Temperature: None°C Interfaces: Parallel Frequency: 400.0MHz Organization (X x Y): 4M x 18 Qualification: Industrial Density: 72.0MBit

Architecture: QDR-II+ Bank Switching: N Burst Length(Words): 4 ECC: N Family: QDR-II+ Frequency: 400.0MHz Lead Ball Finish: Sn/Ag/Cu On-Die Termination: N Operating Temperature: None°C Organization (X x Y): 2Mb x 18 Peak Reflow Temp: 260.0°C Qualification: Industrial Read Latency (Cycles): 2.5 Data Width: x 18 Operating Voltage: NoneV Interfaces: Parallel Density: 36864.0kBit Density: 36.0MBit

Family: QDR-II Lead Ball Finish: Sn/Ag/Cu Operating Temperature: None°C Operating Voltage: NoneV Peak Reflow Temp: 260.0°C Interfaces: Parallel Frequency: 250.0MHz Organization (X x Y): 1M x 18 Qualification: Industrial Density: 18.0MBit

Family: QDR-II Lead Ball Finish: Sn/Ag/Cu Operating Voltage: NoneV Peak Reflow Temp: 260.0°C Operating Temperature: None°C Interfaces: Parallel Frequency: 300.0MHz Organization (X x Y): 4M x 18 Qualification: Commercial Density: 72.0MBit

Family: QDR-II Operating Voltage: NoneV Operating Temperature: None°C Lead Ball Finish: Sn/Ag/Cu Peak Reflow Temp: 260.0°C Interfaces: Parallel Frequency: 300.0MHz Organization (X x Y): 2M x 18 Qualification: Commercial Density: 36.0MBit

Architecture: NoBL, Pipeline Bank Switching: N Data Width: x 36 Family: NoBL Frequency: 167.0MHz Lead Ball Finish: Sn/Pb On-Die Termination: N Operating Temperature: None°C Organization (X x Y): 2Mb x 36 Peak Reflow Temp: 220.0°C Qualification: Industrial Read Latency (Cycles): 1.0 ECC: N Operating Voltage: NoneV Interfaces: Parallel Density: 73728.0kBit Density: 72.0MBit

Architecture: QDR-II Bank Switching: N Burst Length(Words): 2 Data Width: x 9 Family: QDR-II Frequency: 250.0MHz Lead Ball Finish: Sn/Ag/Cu On-Die Termination: N Operating Temperature: None°C Peak Reflow Temp: 260.0°C Qualification: Commercial Read Latency (Cycles): 1.5 ECC: N Organization (X x Y): 16Mb x 9 Operating Voltage: NoneV Interfaces: Parallel Density: 147456.0kBit Density: 144.0MBit

Architecture: QDR-II+ Burst Length(Words): 4 Data Width: x 36 ECC: N Family: QDR-II+ Frequency: 500.0MHz Lead Ball Finish: Sn/Ag/Cu On-Die Termination: N Peak Reflow Temp: 260.0°C Qualification: Industrial Read Latency (Cycles): 2.5 Bank Switching: N Organization (X x Y): 2Mb x 36 Operating Temperature: None°C Operating Voltage: NoneV Interfaces: Parallel Density: 73728.0kBit Density: 72.0MBit

Architecture: Standard Sync, Flow-through Bank Switching: N Burst Length(Words): 4 ECC: N Family: Standard Sync Frequency: 100.0MHz Lead Ball Finish: Pure Sn On-Die Termination: N Operating Temperature: None°C Organization (X x Y): 512Kb x 36 Qualification: Commercial Read Latency (Cycles): 1.0 Data Width: x 36 Peak Reflow Temp: 260.0°C Operating Voltage: NoneV Interfaces: Parallel Density: 18432.0kBit Density: 18.0MBit