Architecture: DDR-II CIO Bank Switching: N Burst Length(Words): 2 Data Width: x 36 ECC: N Lead Ball Finish: Sn/Ag/Cu Operating Temperature max: 85.0°C Organization (X x Y): 1Mb x 36 Peak Reflow Temp: 260.0°C Read Latency (Cycles): 1.5 Family: DDR-II CIO Qualification: Industrial Frequency: 333.0MHz On-Die Termination: N Operating Voltage max: 1.9V Interfaces: Parallel Density: 36.0MBit Density: 36.0MBit

Architecture: Standard Sync, Flow-through Data Width: x 36 ECC: Y Family: Synchronous SRAM with ECC Frequency: 133.0MHz Lead Ball Finish: Ni/Pd/Au Operating Temperature max: 70.0°C Organization (X x Y): 1Mb x 36 Peak Reflow Temp: 260.0°C Qualification: Commercial Read Latency (Cycles): 1.0 Bank Switching: N On-Die Termination: N Operating Voltage max: 3.63V Interfaces: Parallel Density: 36.0MBit

Architecture: DDR-II CIO Bank Switching: N Burst Length(Words): 2 ECC: N Family: DDR-II CIO Frequency: 333.0MHz Lead Ball Finish: Sn/Ag/Cu On-Die Termination: N Operating Temperature max: 70.0°C Organization (X x Y): 8Mb x 18 Qualification: Commercial Read Latency (Cycles): 1.5 Data Width: x 18 Peak Reflow Temp: 260.0°C Operating Voltage max: 1.9V Interfaces: Parallel Density: 144.0MBit

Family: DDR-II CIO Lead Ball Finish: Sn/Ag/Cu Operating Temperature max: 85.0°C Operating Voltage max: 1.9V Peak Reflow Temp: 260.0°C Interfaces: Parallel Frequency: 333.0MHz Organization (X x Y): 2M x 36 Qualification: Industrial Density: 72.0MBit

Architecture: NoBL, Flow-through Bank Switching: N Burst Length(Words): 4 ECC: N Family: NoBL Frequency: 133.0MHz Lead Ball Finish: Pure Sn On-Die Termination: N Organization (X x Y): 1Mb x 18 Qualification: Industrial Read Latency (Cycles): 1.0 Data Width: x 18 Operating Temperature max: 85.0°C Peak Reflow Temp: 260.0°C Operating Voltage max: 3.6V Interfaces: Parallel Density: 18.0MBit

Family: DDR-II CIO Lead Ball Finish: Sn/Ag/Cu Operating Temperature max: 70.0°C Operating Voltage max: 1.9V Peak Reflow Temp: 260.0°C Interfaces: Parallel Frequency: 250.0MHz Organization (X x Y): 1M x 36 Qualification: Commercial Density: 36.0MBit

Family: DDR-II CIO Operating Temperature max: 70.0°C Operating Voltage max: 1.9V Peak Reflow Temp: 260.0°C Lead Ball Finish: Sn/Pb Interfaces: Parallel Frequency: 250.0MHz Organization (X x Y): 2M x 36 Qualification: Commercial Density: 72.0MBit

Architecture: NoBL, Flow-through Bank Switching: N Burst Length(Words): 4 ECC: Y Family: Synchronous SRAM with ECC Frequency: 100.0MHz Lead Ball Finish: Pure Sn On-Die Termination: N Operating Temperature max: 85.0°C Organization (X x Y): 512Kb x 36 Qualification: Industrial Peak Reflow Temp: 260.0°C Data Width: x 36 Read Latency (Cycles): 1.0 Operating Voltage max: 3.6V Interfaces: Parallel Density: 18.0MBit

Architecture: DDR-II+ CIO, ODT Burst Length(Words): 2 Data Width: x 36 Family: DDR-II+ CIO, ODT Frequency: 450.0MHz Lead Ball Finish: Sn/Pb On-Die Termination: Y Operating Temperature max: 85.0°C Organization (X x Y): 4Mb x 36 Peak Reflow Temp: 260.0°C Qualification: Industrial ECC: N Bank Switching: N Read Latency (Cycles): 2.5 Operating Voltage max: 1.9V Interfaces: Parallel Density: 144.0MBit

Lead Ball Finish: Ni/Pd/Au Operating Temperature: None°C Operating Voltage(VCCQ): NoneV Operating Voltage: NoneV Organization (X x Y): 256K x 16 Peak Reflow Temp: 260.0°C Speed: 45.0ns Qualification: Industrial Interfaces: Parallel Family: MoBL™ SRAM Density: 4096.0kBit