Bank Switching: N Burst Length(Words): 4 Data Width: x 36 Family: Synchronous SRAM with ECC Frequency: 133.0MHz Lead Ball Finish: Pure Sn On-Die Termination: N Operating Temperature max: 85.0°C Organization (X x Y): 512Kb x 36 Peak Reflow Temp: 260.0°C Qualification: Industrial Architecture: Standard Sync, Flow-through ECC: Y Read Latency (Cycles): 1.0 Operating Voltage max: 3.6V Interfaces: Parallel Density: 18.0MBit

Architecture: DDR-II CIO Bank Switching: N Burst Length(Words): 2 Data Width: x 36 ECC: N Lead Ball Finish: Sn/Ag/Cu On-Die Termination: N Organization (X x Y): 1Mb x 36 Peak Reflow Temp: 260.0°C Qualification: Industrial Read Latency (Cycles): 1.5 Family: DDR-II CIO Operating Temperature max: 85.0°C Frequency: 250.0MHz Operating Voltage max: 1.9V Interfaces: Parallel Density: 36.0MBit Density: 36.0MBit

Architecture: NoBL, Flow-through Burst Length(Words): 4 Data Width: x 36 ECC: Y Frequency: 133.0MHz Lead Ball Finish: Pure Sn Operating Temperature max: 85.0°C Organization (X x Y): 512Kb x 36 Peak Reflow Temp: 260.0°C Qualification: Industrial Read Latency (Cycles): 1.0 Bank Switching: N Family: Synchronous SRAM with ECC On-Die Termination: N Operating Voltage max: 3.6V Interfaces: Parallel Density: 18.0MBit

Family: DDR-II CIO Lead Ball Finish: Sn/Ag/Cu Operating Temperature max: 70.0°C Peak Reflow Temp: 260.0°C Operating Voltage max: 1.9V Interfaces: Parallel Frequency: 250.0MHz Organization (X x Y): 2M x 36 Qualification: Commercial Density: 72.0MBit

Architecture: DDR-II+ CIO, ODT Burst Length(Words): 2 Data Width: x 36 Family: DDR-II+ CIO, ODT Lead Ball Finish: Sn/Ag/Cu On-Die Termination: Y Operating Temperature max: 85.0°C Organization (X x Y): 2Mb x 36 Peak Reflow Temp: 260.0°C Qualification: Industrial Read Latency (Cycles): 2.5 ECC: N Bank Switching: N Frequency: 550.0MHz Operating Voltage max: 1.9V Interfaces: Parallel Density: 72.0MBit

Architecture: DDR-II+ CIO, ODT Bank Switching: N Burst Length(Words): 2 ECC: N Family: DDR-II+ CIO, ODT Frequency: 550.0MHz Lead Ball Finish: Sn/Pb On-Die Termination: Y Operating Temperature max: 85.0°C Organization (X x Y): 4Mb x 36 Peak Reflow Temp: 260.0°C Qualification: Industrial Read Latency (Cycles): 2.5 Data Width: x 36 Operating Voltage max: 1.9V Interfaces: Parallel Density: 144.0MBit

Family: QDR-II+ Lead Ball Finish: Sn/Ag/Cu Operating Voltage: NoneV Operating Temperature: None°C Peak Reflow Temp: 260.0°C Interfaces: Parallel Frequency: 450.0MHz Organization (X x Y): 4M x 18 Qualification: Industrial Density: 72.0MBit

Family: QDR-II Lead Ball Finish: Sn/Ag/Cu Operating Voltage: NoneV Operating Temperature: None°C Peak Reflow Temp: 260.0°C Interfaces: Parallel Frequency: 250.0MHz Organization (X x Y): 1M x 36 Qualification: Commercial Density: 36.0MBit

Architecture: QDR-II Bank Switching: N Burst Length(Words): 2 Data Width: x 36 Family: QDR-II Lead Ball Finish: Sn/Ag/Cu On-Die Termination: N Operating Temperature: None°C Organization (X x Y): 2Mb x 36 Peak Reflow Temp: 260.0°C Read Latency (Cycles): 1.5 Frequency: 300.0MHz ECC: N Qualification: Industrial Operating Voltage: NoneV Interfaces: Parallel Density: 73728.0kBit Density: 72.0MBit

Family: QDR-II Operating Temperature: None°C Operating Voltage: NoneV Peak Reflow Temp: 260.0°C Lead Ball Finish: Sn/Ag/Cu Interfaces: Parallel Frequency: 300.0MHz Organization (X x Y): 2M x 18 Qualification: Commercial Density: 36.0MBit