Bank Switching: N Burst Length(Words): 2 Data Width: x 18 ECC: N Family: DDR-II+ CIO, ODT Frequency: 550.0MHz Lead Ball Finish: Sn/Ag/Cu Operating Temperature max: 70.0°C Peak Reflow Temp: 260.0°C Qualification: Commercial Read Latency (Cycles): 2.5 Architecture: DDR-II+ CIO, ODT Organization (X x Y): 4Mb x 18 On-Die Termination: Y Operating Voltage max: 1.9V Interfaces: Parallel Density: 72.0MBit

Bank Switching: N Data Width: x 36 ECC: Y Frequency: 200.0MHz Lead Ball Finish: Ni/Pd/Au On-Die Termination: N Operating Temperature max: 70.0°C Organization (X x Y): 1Mb x 36 Peak Reflow Temp: 260.0°C Qualification: Commercial Read Latency (Cycles): 1.0 Family: Synchronous SRAM with ECC Architecture: NoBL, Pipeline Operating Voltage max: 3.63V Interfaces: Parallel Density: 36.0MBit

Architecture: DDR-II+ CIO Bank Switching: N Burst Length(Words): 2 Data Width: x 36 Family: DDR-II+ CIO Frequency: 450.0MHz Lead Ball Finish: Sn/Pb On-Die Termination: N Operating Temperature max: 70.0°C Organization (X x Y): 4Mb x 36 Qualification: Commercial Read Latency (Cycles): 2.0 ECC: N Peak Reflow Temp: 260.0°C Operating Voltage max: 1.9V Interfaces: Parallel Density: 144.0MBit

Architecture: DDR-II CIO Bank Switching: N Burst Length(Words): 2 ECC: N Family: DDR-II CIO Frequency: 333.0MHz Lead Ball Finish: Sn/Ag/Cu On-Die Termination: N Operating Temperature max: 85.0°C Organization (X x Y): 4Mb x 36 Peak Reflow Temp: 260.0°C Qualification: Industrial Read Latency (Cycles): 1.5 Data Width: x 36 Operating Voltage max: 1.9V Interfaces: Parallel Density: 144.0MBit

Family: DDR-II CIO Lead Ball Finish: Sn/Ag/Cu Operating Temperature max: 70.0°C Operating Voltage max: 1.9V Peak Reflow Temp: 260.0°C Interfaces: Parallel Frequency: 300.0MHz Organization (X x Y): 2M x 18 Qualification: Commercial Density: 36.0MBit

Architecture: Standard Sync, Flow-through Bank Switching: N Burst Length(Words): 4 Data Width: x 36 Family: Synchronous SRAM with ECC Lead Ball Finish: Pure Sn On-Die Termination: N Operating Temperature max: 85.0°C Organization (X x Y): 512Kb x 36 Peak Reflow Temp: 260.0°C Read Latency (Cycles): 1.0 ECC: Y Frequency: 133.0MHz Qualification: Industrial Operating Voltage max: 3.6V Interfaces: Parallel Density: 18.0MBit

Family: DDR-II CIO Lead Ball Finish: Sn/Pb Operating Temperature max: 70.0°C Operating Voltage max: 1.9V Peak Reflow Temp: 260.0°C Interfaces: Parallel Frequency: 250.0MHz Organization (X x Y): 2M x 36 Qualification: Commercial Density: 72.0MBit

Lead Ball Finish: Sn/Ag/Cu Operating Temperature: None°C Peak Reflow Temp: 260.0°C Operating Voltage: NoneV Interfaces: Parallel Family: MoBL™ SRAM Organization (X x Y): 2M x 8 Qualification: Industrial Density: 16.0MBit

Bank Switching: N Data Width: x 36 ECC: Y Family: Synchronous SRAM with ECC Frequency: 133.0MHz Lead Ball Finish: Ni/Pd/Au On-Die Termination: N Peak Reflow Temp: 260.0°C Qualification: Industrial Read Latency (Cycles): 1.0 Organization (X x Y): 1Mb x 36 Operating Temperature max: 85.0°C Architecture: Standard Sync, Flow-through Operating Voltage max: 3.63V Interfaces: Parallel Density: 36.0MBit

Architecture: DDR-II CIO Bank Switching: N Burst Length(Words): 2 ECC: N Family: DDR-II CIO Frequency: 333.0MHz On-Die Termination: N Organization (X x Y): 2Mb x 36 Peak Reflow Temp: 260.0°C Qualification: Commercial Read Latency (Cycles): 1.5 Operating Temperature max: 70.0°C Data Width: x 36 Lead Ball Finish: Sn/Ag/Cu Operating Voltage max: 1.9V Interfaces: Parallel Density: 72.0MBit