Architecture: Standard Sync, Pipeline SCD Bank Switching: N Data Width: x 36 ECC: N Lead Ball Finish: Pure Sn On-Die Termination: N Operating Temperature: None°C Organization (X x Y): 2Mb x 36 Qualification: Commercial Read Latency (Cycles): 1.0 Frequency: 200.0MHz Family: Standard Sync Peak Reflow Temp: 260.0°C Operating Voltage: NoneV Interfaces: Parallel Density: 73728.0kBit Density: 72.0MBit

Architecture: NoBL, Flow-through Bank Switching: N Family: NoBL Frequency: 133.0MHz Lead Ball Finish: Sn/Pb On-Die Termination: N Operating Temperature: None°C Organization (X x Y): 2Mb x 36 Peak Reflow Temp: 220.0°C Qualification: Industrial ECC: N Data Width: x 36 Operating Voltage: NoneV Interfaces: Parallel Density: 73728.0kBit Density: 72.0MBit

Architecture: QDR-II Bank Switching: N Burst Length(Words): 2 Data Width: x 36 Family: QDR-II Frequency: 250.0MHz Lead Ball Finish: Sn/Pb On-Die Termination: N Operating Temperature: None°C Organization (X x Y): 4Mb x 36 Peak Reflow Temp: 260.0°C Qualification: Industrial Read Latency (Cycles): 1.5 ECC: N Operating Voltage: NoneV Interfaces: Parallel Density: 147456.0kBit Density: 144.0MBit

Bank Switching: N Data Width: x 18 ECC: N Frequency: 133.0MHz Lead Ball Finish: Ni/Pd/Au On-Die Termination: N Operating Temperature: None°C Organization (X x Y): 2Mb x 18 Peak Reflow Temp: 260.0°C Qualification: Commercial Read Latency (Cycles): 1.0 Family: NoBL Architecture: NoBL, Flow-through Operating Voltage: NoneV Interfaces: Parallel Density: 36864.0kBit Density: 36.0MBit

Architecture: NoBL, Pipeline Bank Switching: N Data Width: x 18 ECC: N Family: NoBL Lead Ball Finish: Pure Sn Operating Temperature: None°C Peak Reflow Temp: 260.0°C Qualification: Commercial Read Latency (Cycles): 1.0 Organization (X x Y): 4Mb x 18 On-Die Termination: N Frequency: 200.0MHz Operating Voltage: NoneV Interfaces: Parallel Density: 73728.0kBit Density: 72.0MBit

Lead Ball Finish: Sn/Ag/Cu Operating Temperature: None°C Operating Voltage: NoneV Peak Reflow Temp: 260.0°C Family: QDR-II Interfaces: Parallel Frequency: 250.0MHz Organization (X x Y): 2M x 36 Qualification: Commercial Density: 72.0MBit

Architecture: QDR-II+, ODT Burst Length(Words): 4 Data Width: x 36 Family: QDR-II+, ODT Frequency: 550.0MHz Lead Ball Finish: Sn/Ag/Cu On-Die Termination: Y Operating Temperature: None°C Organization (X x Y): 1Mb x 36 Qualification: Industrial Read Latency (Cycles): 2.5 Peak Reflow Temp: 260.0°C ECC: N Bank Switching: N Operating Voltage: NoneV Interfaces: Parallel Density: 36864.0kBit Density: 36.0MBit

Architecture: Standard Sync, Pipeline SCD Bank Switching: N Data Width: x 36 ECC: N Frequency: 200.0MHz Lead Ball Finish: Pure Sn;Ni/Pd/Au On-Die Termination: N Operating Temperature: None°C Organization (X x Y): 256Kb x 36 Peak Reflow Temp: 260.0°C Read Latency (Cycles): 1.0 Family: Standard Sync Qualification: Commercial Operating Voltage: NoneV Interfaces: Parallel Density: 9216.0kBit Density: 9.0MBit

Bank Switching: Y Burst Length(Words): 2 Data Width: x 36 ECC: Y Family: QDR-IV Frequency: 1066.0MHz Lead Ball Finish: Sn/Ag/Cu Operating Temperature: None°C Organization (X x Y): 2Mb x 36 Qualification: Commercial Read Latency (Cycles): 8.0 Peak Reflow Temp: 260.0°C Architecture: QDR-IV On-Die Termination: Y Operating Voltage: NoneV Interfaces: Parallel Density: 73728.0kBit Density: 72.0MBit

Family: QDR-II+, ODT Lead Ball Finish: Sn/Ag/Cu Operating Temperature: None°C Operating Voltage: NoneV Peak Reflow Temp: 260.0°C Interfaces: Parallel Frequency: 400.0MHz Organization (X x Y): 2Mb x 36 Qualification: Commercial Density: 72.0MBit