Bank Switching: Y Burst Length(Words): 2 ECC: Y Family: QDR-IV Frequency: 1066.0MHz Lead Ball Finish: Sn/Ag/Cu On-Die Termination: Y Operating Temperature: None°C Organization (X x Y): 8Mb x 18 Peak Reflow Temp: 260.0°C Qualification: Commercial Data Width: x 18 Architecture: QDR-IV Read Latency (Cycles): 8.0 Operating Voltage: NoneV Interfaces: Parallel Density: 147456.0kBit Density: 144.0MBit

Family: QDR-II Lead Ball Finish: Sn/Ag/Cu Operating Temperature: None°C Operating Voltage: NoneV Peak Reflow Temp: 260.0°C Interfaces: Parallel Frequency: 250.0MHz Organization (X x Y): 2M x 36 Qualification: Commercial Density: 72.0MBit

Architecture: QDR-IV Bank Switching: Y ECC: Y Family: QDR-IV Frequency: 1066.0MHz Lead Ball Finish: Sn/Ag/Cu On-Die Termination: Y Operating Temperature: None°C Organization (X x Y): 4Mb x 36 Peak Reflow Temp: 260.0°C Qualification: Commercial Read Latency (Cycles): 8.0 Data Width: x 36 Burst Length(Words): 2 Operating Voltage: NoneV Interfaces: Parallel Density: 147456.0kBit Density: 144.0MBit

Architecture: Standard Sync, Flow-through Bank Switching: N Data Width: x 36 ECC: N Family: Standard Sync Frequency: 133.0MHz Operating Temperature: None°C Qualification: Industrial Read Latency (Cycles): 1.0 Peak Reflow Temp: 260.0°C On-Die Termination: N Organization (X x Y): 2Mb x 36 Lead Ball Finish: Pure Sn Operating Voltage: NoneV Interfaces: Parallel Density: 73728.0kBit Density: 72.0MBit

Architecture: QDR-II+, ODT Bank Switching: N Burst Length(Words): 4 ECC: N Family: QDR-II+, ODT Lead Ball Finish: Sn/Ag/Cu On-Die Termination: Y Operating Temperature: None°C Organization (X x Y): 4Mb x 36 Peak Reflow Temp: 260.0°C Qualification: Industrial Read Latency (Cycles): 2.5 Data Width: x 36 Frequency: 400.0MHz Operating Voltage: NoneV Interfaces: Parallel Density: 147456.0kBit Density: 144.0MBit

Bank Switching: N ECC: N Family: Standard Sync Lead Ball Finish: None On-Die Termination: N Operating Voltage(VCCQ): NoneV Organization (X x Y): 512Kb x 18 Qualification: Industrial Read Latency (Cycles): 1.0 Operating Voltage: NoneV Architecture: Standard Sync, Pipeline SCD Operating Temperature: None°C Data Width: x 18 Interfaces: Parallel Density: 9216.0kBit Density: 9.0MBit

Architecture: Standard Sync, Flow-through Bank Switching: N ECC: N Frequency: 100.0MHz Lead Ball Finish: Ni/Pd/Au On-Die Termination: N Operating Temperature: None°C Peak Reflow Temp: 260.0°C Organization (X x Y): 256Kb x 36 Data Width: x 36 Operating Voltage: NoneV Interfaces: Parallel Density: 9216.0kBit Density: 9.0MBit Qualification: Automotive

Family: QDR-II Lead Ball Finish: Sn/Ag/Cu Operating Voltage: NoneV Peak Reflow Temp: 260.0°C Operating Temperature: None°C Interfaces: Parallel Frequency: 250.0MHz Organization (X x Y): 4M x 18 Qualification: Commercial Density: 72.0MBit

Architecture: Standard Sync, Flow-through Bank Switching: N Data Width: x 36 ECC: N Frequency: 133.0MHz Lead Ball Finish: Ni/Pd/Au On-Die Termination: N Operating Temperature: None°C Peak Reflow Temp: 260.0°C Read Latency (Cycles): 1.0 Family: Standard Sync Qualification: Commercial Organization (X x Y): 1Mb x 36 Operating Voltage: NoneV Interfaces: Parallel Density: 36864.0kBit Density: 36.0MBit

Architecture: NoBL, Pipeline Bank Switching: N Burst Length(Words): 4 ECC: N Family: NoBL Frequency: 167.0MHz Lead Ball Finish: Pure Sn On-Die Termination: N Operating Temperature: None°C Organization (X x Y): 1Mb x 18 Qualification: Industrial Read Latency (Cycles): 2.0 Data Width: x 18 Peak Reflow Temp: 260.0°C Operating Voltage: NoneV Interfaces: Parallel Density: 18432.0kBit Density: 18.0MBit